EDI8G32512V 512kx32 sram module 1 EDI8G32512V rev. 0 1/98 eco #9696 a?-a18 address inputs e?-e3 chip enables w write enable g output enable dq?-dq31 common data input/output vcc power (+3.3v10%) vss ground nc no connection features 512kx32 bit cmos static random access memory ? access times: 15, 17 and 20ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o high density package ? 72 pin zip, no. 173 ? 72 lead simm, no. 174 ? common data inputs and outputs single +3.3v (10%) supply operation the EDI8G32512V is a high speed 16 megabit static ram module organized as 512k words by 32 bits. this module is constructed from four 512kx8 static rams in soj packages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. the EDI8G32512V is offered in gold plated 72 pin zip and 72 lead simm packages, which enable 16 megabits of memory to be placed in less than 1.3 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 3.3v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. pins pd1- pd4, are used to identify module memory density in applications where alternate modules can be interchanged. nc pd3 vss pd2 dq8 dq9 dq10 dq11 a? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1 e3 a17 g dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a18 nc nc pd4 pd1 dq? dq1 dq2 dq3 vcc a7 a8 a9 dq4 dq5 dq6 dq7 w a14 e? e2 a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss nc nc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 pd1, pd2,pd4 = open pd3 = vss a?-a18 w g e? e1 e2 e3 dq?-dq7 dq8-dq15 dq16-dq23 dq24-dq31 19 8 8 8 8 pin configurations and block diagram pin names 512kx32 static ram cmos, high speed module electronic designs incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com advanced
2 EDI8G32512V rev. 0 1/98 eco #9696 EDI8G32512V 512kx32 sram module absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min typ* max units operating power supply current icc1 w, e = vil, ii/o = 0ma, min cycle 640 ma standby (ttl) power supply current icc2 e >vih, vin vih 200 ma full standby power supply current icc3 e >vcc-0.2v 40 ma cmos vin >vcc-0.2v or vin < 0.2v input leakage current ili vin = 0v to vcc -- -- 20 a output leakage current ilo v i/o = 0v to vcc -- -- 20 a output high voltage voh ioh = -4.0ma 2.4 -- -- v output low voltage vol iol = 8.0ma -- -- 0.4 v capacitance truth table (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ci 45 pf data lines cd/q 20 pf chip enable line cc 20 pf write line cn 45 pf ac test conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter sym min typ max units supply voltage vcc 3.0 3.3 3.6 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc +0.3 v input low voltage vil -0.3 -- 0.8 v (note: for tehqz,tghqz and twlqz, cl = 5pf) input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf voltage on any pin relative to vss -0.5v to 4.6v operating temperature ta (ambient) commercial 0c to +70c storage temperature, plastic -55c to +125c power dissipation 2.5 watts output current 20 ma *typical: ta = 25c, vcc = 5.0v e w g mode output power h x x standby high z icc2/icc3 l h l read dout icc1 l l x write din icc1 output l h h deselect high z icc1 these parameters are sampled, not 100% tested.
EDI8G32512V 512kx32 sram module 3 EDI8G32512V rev. 0 1/98 eco #9696 ac characteristics read cycle symbol 15ns 17ns 20ns parameter jedec alt. min max min max min max read cycle time tavav trc 15 17 20 address access time tavqv taa 15 17 20 chip enable access telqv tacs 15 17 20 chip enable to output in low z (1) telqx tclz 3 3 3 chip disable to output in high z (1) tehqz tchz 7 7 10 output hold from address change tavqx toh 3 3 3 output enable to output valid tglqv toe 7 7 8 output enable to output in low z (1) tglqx tolz 0 0 0 output disable to output in high z(1) tghqz tohz 7 7 8 read cycle 2 - w high read cycle 1 - w high, g, e low notes 1. parameter guaranteed, but not tested. tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
4 EDI8G32512V rev. 0 1/98 eco #9696 EDI8G32512V 512kx32 sram module notes: 1. parameter guaranteed, but not tested. symbol 15ns 17ns 20ns parameter jedec alt. min max min max min max write cycle time t avav twc 15 17 20 chip enable to end of write telwh tcw 10 12 15 twleh tcw 10 12 15 address setup time tavwl tas 0 0 0 tavel tas 0 0 0 address valid to end of write tavwh taw 10 12 15 taveh taw 10 12 15 write pulse width twlwh twp 10 12 15 teleh twp 10 12 15 write recovery time twhax twr 0 0 0 tehax twr 0 0 0 data hold time twhdx tdh 0 0 0 tehdx tdh 0 0 0 write to output in high z (1) twlqz twhz 0 7 0 8 0 8 data to write time tdvwh tdw 7 8 9 tdveh tdw 7 8 9 output active from end of write (1) twhqx twlz 2 2 3 ac characteristics write cycle write cycle 1 - w controlled a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax
EDI8G32512V 512kx32 sram module 5 EDI8G32512V rev. 0 1/98 eco #9696 write cycle 2 - e controlled part number speed package (ns) no. EDI8G32512V15mzc 15 173 EDI8G32512V17mzc 17 173 EDI8G32512V20mzc 20 173 ordering information part number speed package (ns) no. EDI8G32512V15mmc 15 174 EDI8G32512V17mmc 17 174 EDI8G32512V20mmc 20 174 package description .032 .032 .022 .060 .018 3.865 max. 0.600 .100 typ. .050 typ. .100 typ . .273 max. max. max. a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh package no. 173 72 pin zip (gold plated leads) package no. 174 72 lead simm (gold plated contacts)
6 EDI8G32512V rev. 0 1/98 eco #9696 EDI8G32512V 512kx32 sram module electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 4mx32 2mx32 1mx32 512kx32 256kx32 128kx32 x32 pinout map for 72 pin zip package configurations nc pd ? dq ? dq1 dq2 dq3 vcc a7 a8 a9 a10 dq4 dq5 dq6 dq7 w\ a14 e ?\ e2\ a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss a19 a21 top view nc pd 2 vss pd1 dq8 dq9 dq10 dq11 a ? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1\ e3\ a17 g\ dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a18 nc 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 nc pd ? dq ? dq1 dq2 dq3 vcc a7 a8 a9 a10 dq4 dq5 dq6 dq7 w\ a14 e ?\ e2\ a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss a19 nc nc pd ? dq ? dq1 dq2 dq3 vcc a7 a8 a9 a10 dq4 dq5 dq6 dq7 w\ a14 e ?\ e2\ a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss nc nc nc pd ? dq ? dq1 dq2 dq3 vcc a7 a8 a9 a10 dq4 dq5 dq6 dq7 w\ a14 e ?\ e2\ a16 vss dq16 dq17 dq18 dq19 a10 a11 a12 a13 dq20 dq21 dq22 dq23 vss a19 nc nc pd 2 vss pd1 dq8 dq9 dq10 dq11 a ? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1\ e3\ a17 g\ dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a18 nc nc pd 2 vss pd1 dq8 dq9 dq10 dq11 a ? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1\ e3\ a17 g\ dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a18 a20 nc pd 2 vss pd1 dq8 dq9 dq10 dq11 a ? a1 a2 dq12 dq13 dq14 dq15 vss a15 e1\ e3\ a17 g\ dq24 dq25 dq26 dq27 a3 a4 a5 vcc a6 dq28 dq29 dq30 dq31 a18 a20
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